Industrial Temperature and NAND Flash in SSD Products | EEWeb

Industrial Temperature and NAND Flash in SSD Products

Introduction
Many NAND flash based SSD products on the market today are touted as “Industrial Grade” or as supporting “Industrial Temperature” (typically -40?C to 85?C) operation. These SSD products are typically screen-tested for functionality across the temperature range prior to shipment. The effects of temperature on the data retention and endurance of the SSD, however, is rarely specified or discussed.

The ability of NAND flash to store and retain data depends on the temperature which the NAND flash is subjected to during writing, and between the time the data is written to the time the data is read. The higher the temperature that the NAND flash experiences, the greater the acceleration of charge de-trapping mechanisms that could lead to random data bit failures. NAND endurance is also impacted since endurance has an inverse relationship to data retention, and the rate of wear-out of NAND cells is affected by temperature at the time of programming and erasing NAND. This article describes these effects and provides some direction on the operation of a NAND flash based data storage system when exposed to different temperatures.

NAND Flash Memory
The floating-gate transistor is the building block of all flash technology:

Figure 1 

In the floating-gate transistor, an insulating oxide layer resides between the floating gate and the substrate. When voltage above the cell threshold, (Vt), is applied to the top gate, the transistor is “turned on” and conducts a current. To prevent the transistor from conducting current, electrons are forced through the thin oxide layer by the application of high voltage applied to the top gate. This is the process of writing (or programming) the NAND cell. To erase a cell, the substrate well is raised to a high voltage forcing the electrons back through the oxide layer from the floating gate into the substrate. To read a NAND cell, a voltage above Vt is applied to the top gate and the current flowing in the transistor sensed by a sense amplifier, which gives information about the amount of charge stored in the cell.

Charge De-trapping and Bit Flips
The repeated electron tunneling mechanism from writing and erasing NAND cells causes the buildup of charge traps in the tunnel oxide layer. Some of the traps are deep, and eventually accumulate to the point where the tunnel oxide becomes conductive without application of an input voltage, and the cell is no longer capable of storing charge. At this point, programming the NAND will result in program failures and the entire block must be marked “bad” by the SSD.

Other traps are shallow and as they collect charge, inhibit normal programming of the cell. Shallow traps start de-trapping immediately after the cell is programmed, causing the cell threshold to decrease from the level set through the NAND program algorithm, leading to a potential “bit flip”. In addition, charge naturally de-traps within a NAND cell over time, which is the limiting factor in NAND data retention.

De-trapping of stored charge is accelerated by exposure to high temperature, and the temperature that the NAND flash is subjected to is a critical factor. The Arrhenius equation describes the rate of reaction for a given temperature (T), and activation energy (Ea) and can be used to calculate the acceleration in charge de-trapping for the NAND flash cell.

Figure 2 

Example of Arrhenius Equation calculation in JEDEC NAND standard

JEDEC NAND reliability specification JESD47H, states that a bake time of 10 hours at 125oC is equivalent to 1 year data retention at 55oC
The Arrhenius equation derives an acceleration factor from 55oC to 125oC of 939
10 hours accelerated by a factor of 939 is 9,390 hours ~ 1 year (8,760 hours)

It is important to note that the temperature and duration to which the NAND flash is subjected to after programming is the most critical part in determining the acceleration factor. The acceleration factor for a NAND relative to a temperature of 55oC is shown in the table below. For example, for NAND devices specified with 1 year of data retention, storing at 85oC will accelerate the charge de-trapping mechanism by 26 times when compared to storing at 55oC.

Figure 3 

At the end of life of a NAND cell, when the device has been cycled through the maximum number of program-erase (endurance) cycles as specified by the manufacturer, data loss can occur if the NAND is stored or read over extended periods of time at high temperature. Conversely, when the NAND is stored or read at a lower temperature than 55oC, the acceleration factor becomes less than 1 and the NAND data retention is extended relative to the specification.

It should be noted that at the end of NAND’s rated endurance, the NAND device is usually not in jeopardy of immediate failure. NAND manufacturer’s endurance ratings are typically specified to ensure that the number of bad blocks that occur over time will be within a predictable percentage limit and that the NAND will be able to retain data for 1 year at 55oC in accordance with JESD47H.01. Beyond the endurance limit, blocks may become bad at a faster rate and the data retention capabilities of the drive become diminished. The impact to reliability of the drive is then dependent upon the media management capabilities of the drive controller.

Temperature and Bit Error Rate
Over time, NAND cells may lose enough charge and flip enough bits to overwhelm the ECC capability of the drive controller and cause data loss. Another illustration of the effects of temperature on reliability is the differences in raw bit error rate (RBER) of the NAND when write cycled to a fixed P/E count at different temperatures. WD internal test data shows the following relationship between the RBER and temperature.

Figure 4 

The data shows that NAND programmed to its endurance limit at -40oC will have a higher RBER than NAND programmed at 25oC, and higher than that of NAND programmed at 85oC. The operation of programming NAND at low temperature increases the rate of degradation of the cell oxide layer relative to programming at higher temperature.

Conclusion
NAND is subject to two competing factors relative to temperature. At high temperature, programming and erasing a NAND cell is relatively less stressful to its structure, but data retention of a NAND cell suffers. At low temperature, data retention of the NAND cell is enhanced but the relative stress to the cell structure due to program and erase operations increases.

The effects of temperature apply in varying degrees to all NAND devices from all NAND vendors. Industrial temperature rated NAND devices from the manufacturer are tested for functionality at temperatures of -40?C and 85?C (depending on the NAND manufacturer’s specification), but that does not give these parts higher endurance or greater immunity to the effect of charge de-trapping. Sensitivities to these factors appear to be increasing as NAND process geometries shrink, but the actual endurance and data retention characteristics of a particular NAND device will vary between NAND manufacturers, process materials, and geometries.

Therefore, it behooves the SSD vendor to fully understand the physical characteristics of the NAND chosen for various applications, and to specify SSD products with the different endurance and data retention characteristics seen across the industrial temperature range. At the same time, it is also important for users of NAND flash based SSDs to understand the relationship between temperature, data retention, and endurance; and how their usage models will affect the long term reliability of the SSD.

The best way to optimize the data retention of a NAND-based SSD is to limit the temperature at which the NAND flash is stored. When the drive has reached or is approaching its end of life, limiting the time of exposure to high temperature will also help extend the data retention.