| Process | 7 nm | 5 nm | 5 nm |
| Package | 23 mm × 23 mm × 2.26 mm FCBGA+HS | 25 mm × 25 mm × 2.31 mm FCBGA+HS | 25 mm × 25 mm × 2.25 mm FCBGA+HS |
| BGA pitch | 0.7 mm | 0.6 mm | 0.6 mm |
| AECQ | Grade 3 | Grade 3 | Grade 3 |
| CPU | Qualcomm ? Kryo? 485, 2 MB L3
1 x Gold prime core up to 2.419 GHz
3 x Gold cores up to 2.131 GHz
4 x Silver cores up to 1.785 GHz | Kryo Gen 6, 2 MB L3 per cluster 4 x Gold prime core up to 2.35 GHz 4 x Gold prime core up to 2.35 GHz | Kryo 695, 8 MB L3
4 x Gold prime core up to 2.5 GHz
4 x Gold cores up to 2.05 GHz |
| DMIPS | 105K | 189/230K | 220K |
| Memory | 4 × 16 LPDDR4X; up to 2092.8 MHz | 6 x 16-bit LPDDR5; up to 3200 MHz | 8 × 16 LPDDR4X; up to 2092.8 MHz |
| GPU | Qualcomm ? Adreno? 640 | Adreno 663 | Adreno 695 |
| GPU（GFLOPS） | 1100 | 1100/1200/1300 | 3000 |
| AI/NSP | V66, 4 x Qualcomm ? Hexagon? Vector
eXtensions (Qualcomm ? Hexagon? Vector
eXtensions (HVX)), 1 x HCP, up to 1.459 GHz | V73, four HVX, two HMX, up to 1.5 GHz | V68, 4 x HVX, 2 x HMX, up to 1.4 GHz |
| AI(TOPS) | 8 | 10/15/24/32/48 | 40~50 |
| DPU | Adreno DPU 895, 24 MP, DSC v1.1, up to
530 MHz | Adreno DPU 1199, 48 MP, DSC v1.2, up to 600 MHz | Adreno DPU 1199, 64 MP, DSC v1.2, up
to 600 MHz |
| Camera Processor | Qualcomm Spectra? 380 ISP, 2.5 Gbps/lane,
40 Gbps total | Qualcomm Spectra 690, 2.5 Gbps/lane, 40 Gbps total | Qualcomm Spectra 395, 2.5 Gbps/lane,
40 Gbps total |
| VPU | Adreno VPU 554, decode 4k120, encode 4k60,concurrent 4k60/4k30 decode/encode | Adreno VPU 670, decode 4k240, encode 4k120, concurrent 4k120 decode/encode | Adreno VPU 665, decode 4k240, encode 4k120, concurrent 4k120 decode/encode |
| Audio | V66 512 KB L2 up to 1.459 GHz | V66 2 MB L2 up to 1.459 GHz | V66 2 MB L2 up to 1.459 GHz |
| Security | SPU230 | SPU230 | SPU250 |
Functional
safety | Safety Element out of Context (SEooC)
targeting assumed ASIL B use cases | Safety Element out of Context (SEooC) targeting assumed ASIL B use cases. Contains dedicated Safety Island (SAIL) with quad Cortex-R52 CPU configurable per pair | Safety Element out of Context (SEooC)
targeting assumed ASIL B use cases.
Contains dedicated Safety Manager
sub-system, with lock step core |
| Junction temp | -40°C to +105°C | -40°C to +115°C | -40°C to +115°C |
| Display - DP | 4-lane DisplayPort v1.4 shared with
USB 3.1 Gen 2 | 4 x 4-lane embedded DisplayPort v1.4b | 3 x 4-lane DisplayPort v1.4, 1 x shared with USB
3.1 Gen 2
4 x 4-lane embedded DisplayPort v1.4b |
| Display - DSI | DSI D-PHY v1.2
4-lane DSI0
4-lane DSI1 | DSI D-PHY v1.2 DSI C-PHY v1.1 2 x 4-lane DSI | DSI D-PHY v1.2 DSI C-PHY v1.1 2 x 4-lane DSI |
| Camera – CSI | CSI-2 v1.3
4-lane CSI0
4-lane CSI1
4-lane CSI2
4-lane CSI3 | CSI D-PHY v1.2 CSI C-PHY v1.1 4 x 4-lane CSI | CSI D-PHY v1.2 CSI C-PHY v1.1 4 x 4-lane CSI |
| CCI-I2C | x4 | x8 | x8 |
| Audio – LS-I2S | 4 x 2 data lanes each
1 x 4 data lanes each | 9 x 2 data lanes each 1 x 4 data lanes each | 9 x 2 data lanes each 1 x 4 data lanes each |
| Audio – HS-I2S | 3 x 2 data lanes each, receive only | 5 x 2 data lanes each, receive only | 5 x 2 data lanes each, receive only |
| Audio – TDM/PCM | 4 x 2 data lanes each
1 x 4 data lanes each | 9 x 2 data lanes each 1 x 4 data lanes each | 9 x 2 data lanes each 1 x 4 data lanes each |
| Storage – UFS | 2 lane UFS 2.1 gear 3 rate A | 1 x 2 lane UFS 3.1 gear 4 rate B | 1 x 2 lane UFS 3.1 gear 4 rate B |
| PCIe | 1-lane PCIe 3 (RC)
2-lane PCIe 3 (RC/EP) | 1 x 2-lane PCIe 4 (RC/EP) 1 x 4-lane PCIe 4 (RC/EP) | 1 x 1-lane PCIe 3 (RC/EP)
2 x 4-lane PCIe 3 (RC/EP) |
Ethernet –
RGMII/RMII | 1 x with MDIO 1.8 V only | 2 x SGMII up to 2.5 Gbps | 2 x with MDIO 1.8 V or 2.5 V |
| USB | 1 x USB 3.1 Gen 2 shared with
DisplayPort
1 x USB 3.1 Gen 2 | 2 x USB3.1 Gen 2 1 x USB2.0 | 4 x USB3.1 Gen 2 1x shared with DisplayPort
2 x USB2.0 |
| Functional safety | - | 79 SAIL I/Os * 5 x SAIL QUP SE (UART/I2C/SPI-M/SPI-S) 3 x on-board thermal monitors 1 x RGMII/RMII with MDIO 1.8 V or 2.5 V Eight CAN-FD up to 12 Mbps 1 x Octal-SPI/Quad-SPI NOR (SAIL) | 20 SM-GPIOs
1 x SPI – master
1 x SPI – slave
2 x I2C – master
2-lane UART – master
4 x clock monitors
44 x voltage monitors
3 x on-board thermal monitors |
Miscellaneous
SPI
I 2 C
UART
GPIO | 26 x QUP SE (GPIO + SSC)
Master and slave
Master
Host
174 GPIOs | 21 QUP SE (GPIO) Master and slave Master Multi-master Host 149 GPIOs | 32 x QUP SE (GPIO+SSC)
Master and slave
Master
Host
228 GPIOs |
| PMIC | 20 x GPIOs
3 x AMUX | 35 GPIOs 8 x AMUX | 32 x GPIOs
，7 x AMUX |
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